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VHDL/Xử lý ảnh/Matlap

Huong dan viet testbench


Minh se huong dan cac ban viet file testbench :

Nguồn : Itepress.com  Trang website chuyên về điện tử viễn thông.

 

Minh se lay 1 vi du cu the cho cac ban de hinh dung.Ở đây mình lấy ví dụ với VHDL còn Verilog thi cung tuong tu.Minh se huong dan chi tiet nhu sau:(phai chac chan la ban da cai du Quartus va ModelSim nha)

B1: Dung quartus  tao 1 project voi ten la NOR_ent (Chon ngon ngu VHDL nha cac ban,vi du nay dung VHDL ma).Luu trong 1 thu muc gia su nhu D:\VHDL\NOR_ent  cai nay de teo xem file dem cho viec viet testbench ma.

B2:Tao  mot file moi NOR_ent.vhd

Ví dụ đây là 1 file mình viết sẵn code bằng VHDL(bộ NOR).File nayf luu la NOR_ent.vhd.

————————————————–
–Nor thi neu x=y=0 thi F bang 1
library ieee;
use ieee.std_logic_1164.all;
————————————————–
entity NOR_ent is
port(
x,y:in std_logic;
F:out std_logic
);
end NOR_ent;
—————————————————–
architecture behave1 of NOR_ent is
begin
process(x,y)
begin
if(x=’0′ and y=’0′) then
F<=’1′;
else
F<=’0′;
end if;
end process;
end behave1;
architecture behv2 of NOR_ent is
begin

F <= x nor y;

B3: Tu giao dien cua quartus chon Processing ->Start Compliation (Hoac nhan ctrl + L).Cho khi compliation hoan thanh.

B4: Tu giao dien cua quartus chon Processing->Start->Start Test Bench Template Writer .Cai nay la file dem de viet file testbench.Cac ban chu y den duong dan cua no(ta tim file do roi sua lai).Duong dan voi vi du thu muc tren minh da tao la D:\VHDL\NOR_ent thiduong dan den file dem de viet testbench la

D:/VHDL/NOR_ent/simulation/modelsim/NOR_ent.vht .cac ban sua file NOR_ent.vht nay.No la file dem de viet Testbench.Gio thi ban muon test the nao thif them vao trong file do vi du minh test nhu sau.Minh cung sua file NOR_ent.vht roi luu lai thanh file moi la

NOR_ent_tb.vhd .Ok gio ban da co file testbench roi.Vi du voi truong hop nay minh co code sau (Sau khi da sua file dem o tren NOR_ent.vht )

— Copyright (C) 1991-2011 Altera Corporation
— Your use of Altera Corporation’s design tools, logic functions
— and other software and tools, and its AMPP partner logic
— functions, and any output files from any of the foregoing
— (including device programming or simulation files), and any
— associated documentation or information are expressly subject
— to the terms and conditions of the Altera Program License
— Subscription Agreement, Altera MegaCore Function License
— Agreement, or other applicable license agreement, including,
— without limitation, that your use is for the sole purpose of
— programming logic devices manufactured by Altera and sold by
— Altera or its authorized distributors.  Please refer to the
— applicable agreement for further details.

— ***************************************************************************
— This file contains a Vhdl test bench template that is freely editable to
— suit user’s needs .Comments are provided in each section to help the user
— fill out necessary details.
— ***************************************************************************
— Generated on “03/24/2012 18:11:57”

— Vhdl Test Bench template for design  :  NOR_ent

— Simulation tool : ModelSim-Altera (VHDL)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY NOR_ent_tb IS
END NOR_ent_tb;
ARCHITECTURE NOR_ent_arch OF NOR_ent_tb IS
— constants
— signals
SIGNAL F : STD_LOGIC;
SIGNAL x : STD_LOGIC;
SIGNAL y : STD_LOGIC;
COMPONENT NOR_ent
PORT (
F : OUT STD_LOGIC;
x : IN STD_LOGIC;
y : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : NOR_ent
PORT MAP (
— list connections between master ports and signals
F => F,
x => x,
y => y
);
init : PROCESS
— variable declarations
BEGIN
— code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
— optional sensitivity list
— (        )
— variable declarations
BEGIN
— code executes for every event on sensitivity list
x<=’0′; y<=’0′; wait for 100 ps;
x<=’1′; y<=’1′; wait for 100ps;
x<=’0′; y<=’1′; wait for 100ps;
x<=’1′; y<=’1′; wait for 100ps;
x<=’0′; y<=’0′; wait for 100ps;
WAIT;
END PROCESS always;
END NOR_ent_arch;
——————————————–Het code roi——————————————————————-

Noi them ve cach viet test bench:

Cac ban tuong tuong don gian nhu ta cung cap dau vao cho bo ma minh da tao vi du nhu theo thoi gian,o thoi diem nay thi dau vao se la the nao …Con mot so van de khac nhu them canh bao …

Vi du ve theo su kien:Minh lay voi code tren

x<=’0′; y<=’0′; wait for 100ps;

— Tuc la trong 100 ps thi dau vao cua bo NOR la x=0 va y=0

Vi du ve cac canh bao:cac ban tham khao Mot chuong trinh sau de hieu.Day la code viet cho ALU don gian.Cac ban nghien cuu mot chut la OK.

File thu nhat la ALU.vhd

—————————————————

— ALU stands for arithmatic logic unit.
— It perform multiple operations according to
— the control bits.
— we use 2’s complement subraction in this example
— two 2-bit inputs & carry-bit ignored
—————————————————

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

—————————————————

entity ALU is

port(    A:    in std_logic_vector(1 downto 0);
B:    in std_logic_vector(1 downto 0);
Sel:    in std_logic_vector(1 downto 0);
Res:    out std_logic_vector(1 downto 0)
);

end ALU;

—————————————————

architecture behv of ALU is
begin

process(A,B,Sel)
begin

— use case statement to achieve
— different operations of ALU

case Sel is
when “00” =>
Res <= A + B;
when “01” =>
Res <= A + (not B) + 1;
when “10” =>
Res <= A and B;
when “11” =>
Res <= A or B;
when others =>
Res <= “XX”;
end case;

end process;

end behv;

—————————————————-
File thu 2 la  ALU_TB.vhd

——————————————————————————
— we illustrate how to use package and procedure in this example
— it seems a kind of complex testbench for this simple module,
— the method, however, makes huge circuit testing more complete,
— covenient and managable
——————————————————————————

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

— define constant, signal and procedure within package for ALU

package ALU_package is

constant INTERVAL: TIME := 8 ps;

signal sig_A, sig_B: std_logic_vector(1 downto 0);
signal sig_Sel: std_logic_vector(1 downto 0);
signal sig_Res: std_logic_vector(1 downto 0);

procedure load_data(signal A, B: out std_logic_vector(1 downto 0);
signal Sel: out std_logic_vector(1 downto 0));

procedure check_data(signal Sel: out std_logic_vector( 1 downto 0));

end ALU_package;

— put all the procedure descriptions within package body

package body ALU_package is

procedure load_data (signal A, B: out std_logic_vector(1 downto 0);
signal Sel: out std_logic_vector(1 downto 0) ) is
begin
A <= sig_A;
B <= sig_B;
Sel <= sig_Sel;
end load_data;

procedure check_data (signal Sel: out std_logic_vector( 1 downto 0)) is
begin
Sel <= sig_Sel;
if (sig_Sel=”00″) then
assert(sig_Res = (sig_A + sig_B))
report “Error detected in Addition!”
severity warning;
elsif (sig_Sel=”01″) then
assert(sig_Res = (sig_A – sig_B))
report “Error detected in Subtraction!”
severity warning;
elsif (sig_Sel=”10″) then
assert(sig_Res = (sig_A and sig_B))
report “AND Operation Error!”
severity warning;
elsif (sig_Sel=”11″) then
assert(sig_Res = (sig_A or sig_B))
report “OR operation Error!”
severity warning;
end if;
end check_data;

end ALU_package;

— Test Bench code for ALU
————————————————————————–

library IEEE;
use IEEE.std_logic_1164. all;
use work.ALU_package.all;

entity ALU_TB is            — entity declaration
end ALU_TB;

architecture TB of ALU_TB is

component ALU
port(    A:    in std_logic_vector(1 downto 0);
B:    in std_logic_vector(1 downto 0);
Sel:    in std_logic_vector(1 downto 0);
Res:    out std_logic_vector(1 downto 0)
);
end component;

signal A, B, Res: std_logic_vector(1 downto 0):=”00″;
signal Sel: std_logic_vector(1 downto 0);

begin

U_ALU: ALU port map (A, B, Sel, Res);

process
begin

sig_A <= “10”;
sig_B <= “01”;

sig_Sel <= “00”;            — case 1: Addition
wait for 1 ps;
load_data(A, B, Sel);
wait for 1 ps;
sig_Res <= Res;
wait for INTERVAL;
check_data(Sel);

sig_Sel <= “01”;            — case 2: subtraction
wait for 1 ps;
load_data(A, B, Sel);
wait for 1 ps;
sig_Res <= Res;
wait for INTERVAL;
check_data(Sel);

sig_Sel <= “10”;            — case 3: AND operation
wait for 1 ps;
load_data(A, B, Sel);
wait for 1 ps;
sig_Res <= Res;
wait for INTERVAL;
check_data(Sel);

sig_Sel <= “11”;            — case 4: OR operation
wait for 1 ps;
load_data(A, B, Sel);
wait for 1 ps;
sig_Res <= Res;
wait for INTERVAL;
check_data(Sel);
wait;

end process;

end TB;

————————————————————————-
configuration CFG_TB of ALU_TB is
for TB
end for;
end CFG_TB;
————————————————————————-

Cac ban co the tham khao them 1 so code sau day:

 Driver   Behavior Code Behavior Simulation  Inverter   Behavior Code Behavior Simulation
 OR gate  Behavior Code Behavior Simulation  NOR gate   Behavior Code Behavior Simulation
AND gate Behavior Code Behavior Simulation NAND gate Behavior Code Behavior Simulation
 XOR gate  Behavior Code Behavior Simulation  XNOR gate  Behavior Code Behavior Simulation

 Multiplexor Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
 Decoder Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
 Adder Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
 Comparator Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
 ALU Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
Multiplier Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation

 Simple Latch Behavior Code  Test Bench Behvaior Simulation Gate-level Implementation Gate-level Simulation
D Flip-Flop Behavior Code Test Bench Behavior Simulation Gate-level Implementation Gate-level Simulation
JK Flip-Flop Behavior Code Test Bench Behavior Simulation Gate-level Implementation Gate-level Simulation

 Register Behavior Code  Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Structural Simulation
Shift Register Behavior Code  Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Structural Simulation
 Counter Behavior Code  Test Bench Behavior Simulation Gate-level Implementation Synthesis Schematic Structural Simulation
Combinational Logic Behavior Code Test Bench  Behavior Simulation Synthesis Schematic Gate-level Simulation
Tri-State Driver Behavior Code Test Bench Behavior Simulation Synthesis Schematic Gate-level Simulation
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Discussion

One thought on “Huong dan viet testbench

  1. hay qua cam on ban

    Posted by yeu em nhieu hon cac con khac | May 6, 2012, 10:12 pm

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